Information processing systems adopting image processing technologies and audio processing technologies have higher performances and functions with the increasingly advanced image and audio processing technologies. This is followed by an increase in the circuit size of the hardware of the information processing systems and in the amount of software code thereof.
FIG. 1 is a block diagram showing an example of the configuration of an image processing system in which a dedicated image processing apparatus is connected to a host apparatus (system controller). An information processing system having a high-performance image processing function can be realized with such a configuration using the hardware dedicated to image processing. Referring to FIG. 1, the image processing system includes a host apparatus 10, an image processing apparatus 11, a bridge 12, an external storage apparatus 13, and a synchronous dynamic random access memory (SDRAM) 14. The image processing apparatus 11 includes a host interface 21, which is a serial interface, a demultiplexer (DEMUX) 22 serving as a stream interface, a control central processing unit (CPU) 23, a video processor 24, and a SDRAM interface 25.
In the image processing system in FIG. 1, the host apparatus 10 is connected to the image processing apparatus 11 via the serial interface and the image processing apparatus 11 performs the image processing under the control of the host apparatus 10. In the example of the configuration in FIG. 1, firmware for the image processing is firstly transferred from the host apparatus 10 to the image processing apparatus 11 through a serial port. Then, the image processing apparatus 11 is caused to execute the transferred firmware in order to perform a variety of processing concerning image data. The variety of processing includes transferring image data from the external storage apparatus 13 to the image processing apparatus 11 through the stream interface.
FIG. 2 is a flowchart showing an example of a process of downloading the firmware through the serial interface in the configuration shown in FIG. 1. The firmware is downloaded from the host apparatus 10 to the image processing apparatus 11 in accordance with the process shown in FIG. 2 at startup of the image processing system, and the downloaded firmware is booted up to activate the image processing apparatus 11.
Specifically, after the image processing apparatus 11 is turned on, the control CPU 23 in the image processing apparatus 11 starts to execute a boot loader. The boot loader is a control program stored in a read only memory (ROM) 26 (refer to FIG. 1) connected to the control CPU 23. The control CPU 23 firstly executes the control program after the image processing apparatus 11 is turned on.
Referring to FIG. 2, in Step S1, the execution of the boot loader causes the control CPU 23 to assert an interruption signal to an interruption terminal of the host apparatus 10 through the host interface 21. In Step S2, the host apparatus 10 waits for an interruption while determining whether an interruption occurs. If an interruption from the image processing apparatus 11 occurs, then in Step S3, the host apparatus 10 transfers the firmware to the image processing apparatus 11 through the serial port in response to the interruption. Specifically, the host apparatus 10 reads out the firmware from the external storage apparatus 13 and transfers the readout firmware to the image processing apparatus 11 through the serial port.
FIG. 3 illustrates an example of the format of the firmware to be downloaded. Referring to FIG. 3, firmware 30 includes a header part 31 and multiple data block parts 32-1 to 32-n (n denotes an integer that is equal to two or more). The header part 31 includes an entry address 33 and a block count 34 in its header area. The entry address 33 indicates the execution start address of the firmware stored in the memory area. The block count 34 indicates the number n of blocks. Each of the data block parts 32-1 to 32-n includes a top address 35 and a byte count 36 in its block header area. The top address 35 indicates the address where the corresponding data block part is positioned in the memory area. The byte count 36 indicates the amount of data in the body of the corresponding data block part (the data section) in units of bytes.
Referring back to FIG. 2, in Step S4, the control CPU 23 that is executing the boot loader analyzes the firmware 30 (serial data) received through the host interface 21, which is the serial interface. In Step S5, the control CPU 23 transfers the firmware body in the data section of the corresponding data block to the top address 35 set in the header of each of the data block parts 32-1 to 32-n based on the result of the analysis. Specifically, the control CPU 23 writes the data in the firmware in the SDRAM 14 through the SDRAM interface 25. In Step S6, the control CPU 23 determines whether the reception of the firmware including the amount of data specified in the block count 34 and the byte count 36 in the firmware 30 is completed or not based on the result of the analysis.
When the reception of the firmware is completed, then in Step S7, the control is moved from the boot loader to the firmware. Specifically, the control CPU 23 sets a program pointer at the execution start address indicated by the entry address 33 in the header part 31 in the firmware 30 to start execution of the firmware. In Step S8, the execution of the firmware causes the control CPU 23 to assert an interruption signal to the interruption terminal of the host apparatus 10 through the host interface 21. The image processing apparatus 11 notifies the host apparatus 10 of the completion of the boot-up with the interruption. The host apparatus 10 starts certain processing in response to the notification of the completion of the boot-up.
A serial communication interface, such as a general-purpose RS-232C/UART/I2C, is generally used as the serial interface through which the firmware 30 is downloaded in the above configuration. However, since the data transfer speed of such a serial communication interface is relatively low, there is a problem in that it takes a longer time to download the firmware when the performance of the information processing apparatus is improved to increase the size of the firmware. Although the firmware may be downloaded from, for example, an external-attached flash memory, the number of pins and/or the cost of the parts are undesirably increased in such a configuration.
Such a technology is disclosed in, for example, Japanese Laid-open Patent Publication No. 2007-72532.